PCI-Express (PCIe) is the successor of the PCI (Peripheral Component Interconnect) technology which is the most widely used interconnect standard between processors, e.g., CPUs, and their peripherals deployed within desktop computers and servers. The PCI bus is well regarded for its high throughput, low-latency, packet-based and switched interconnection technology.
PCIe is a serial connection that operates more like a network coupling than a serial bus interface. For instance, instead of one bus that handles data from multiple sources, the PCIe bus has a switch that controls several point-to-point serial connections. These connections are multiplexed out from the switch and connect directly to devices where the data is to be sent. Every device has its particular dedicated connection, so devices no longer share bandwidth, which is different from normal bus operations.
Currently, PCIe is mostly deployed within single enclosure machines (e.g., servers and PCs) and primarily at the level of the printed circuit board (PCB). With all its attributes and advantages, PCIe can clearly become a flexible and cost efficient alternative to current data center interconnect technologies, such as Ethernet (ETH) and InfiniBand (IB).
With the development of multi-processor devices, there is a need for better memory utilization particularly with respect to address allocation space. Initially, when a host device is powered up, it is not aware of the system topology, so it performs discovery to learn what devices are present and how to map them in its memory space. To support standard discovery and configuration software, the PCI specification defines a standard format for the control and status registers. With multi-processors, system designers developed end points with their own native processors built-in. This practice causes a problem in that both the host processor and the intelligent adapters in PCIe (upon power up) would attempt to enumerate the entire system thereby causing system conflicts and may ultimately result in a non-functional system. As a result, non-transparent bridges (NTB) were developed which appear as endpoints to the discovery processes, thereby eliminating these software conflicts.
In light of the above descriptions, with more sophisticated node topologies, there is a need for better intelligent discovery mechanisms to map address spaces more efficiently. More specifically, with the advent of NTB bridges, there is a need to translate addresses from one memory space to another, hence any optimization of address allocation in the discovery stage would provide for a more overall robust and reliable PCIe architecture.